International Research Journal of Education and Technology

Error-tolerant computing has become a cornerstone in the development of efficient digital circuits, especially in domains such as multimedia processing, where minor inaccuracies are permissible. This paper explores the replacement of traditional static CMOS logic with dynamic CMOS logic in Error-Tolerant Adders (ETAs) to enhance power efficiency and computational speed. Using Synopsys tools such as Design Compiler and HSPICE, the proposed architectures were designed and simulated to evaluate key metrics such as power consumption, delay, and error tolerance. The results demonstrate up to 38% power reduction and 30% improvement in delay compared to static CMOS adders. This makes dynamic CMOS ETAs particularly suitable for low-power, high-speed applications. Keywords— Dynamic CMOS Logic, Error-Tolerant Adders, Power-Delay Product, Synopsys Tools, Low-Power Applications.