International Research Journal of Education and Technology

The relentless scaling of CMOS technology has exacerbated power dissipation challenges in VLSI circuits, necessitating innovative low-power design techniques. This paper proposes an integrated approach combining Gate Diffusion Input (GDI) and Static Power Adiabatic Differential Logic (SPADL) to achieve significant reductions in power consumption while maintaining performance. The methodology involves designing combinational and sequential circuits using the hybrid GDI-SPADL topology, evaluated through SPICE simulations at 180nm technology node. Key findings include up to 60% reduction in power-delay product (PDP) compared to conventional static CMOS, with detailed analyses of energy recovery, delay, and scalability. The work highlights the potential of adiabatic principles in GDI-based designs for energy-efficient applications in portable and IoT devices.

The escalating demand for energy-efficient computing in an era dominated by portable electronics, Internet of Things (IoT) devices, wearable technology, and edge artificial intelligence has placed unprecedented pressure on traditional CMOS-based VLSI design paradigms. As semiconductor technology scales into deep submicron and nanoscale regimes, the limitations of conventional static CMOS logic—particularly its quadratic dependence of dynamic power on supply voltage, high transistor overhead, and vulnerability to leakage currents—have become critical bottlenecks. This research has systematically addressed these challenges by proposing, analyzing, and validating a novel hybrid logic style that integrates the Gate Diffusion Input (GDI) technique with Static Power Adiabatic Differential Logic (SPADL), resulting in a low-power, high-performance digital design methodology tailored for power-constrained environments.

Keywords: Low-power VLSI, GDI technique, SPADL logic, adiabatic computing, power-delay product, CMOS scaling.